AMD Instinct MI100
The MI100 introduced AMD's CDNA architecture with Matrix Cores for AI acceleration. A capable HPC and ML accelerator with 32GB HBM2 memory at competitive power efficiency.
VRAM
32 GB
Memory
HBM2
Bandwidth
1,229 GB/s
FP16
184.6 TF
TDP
300 W
Memory and compute
Architecture and power
Notes
First CDNA architecture GPU. Optimized for HPC and ML workloads.
Models that may fit on AMD Instinct MI100
Estimates based on INT8 quantization. Actual fit depends on framework and batch size.
More GPUs by AMD
The manufacturer's other cards in the catalog, largest memory first, with bandwidth and power where published.
Frequently asked questions about AMD Instinct MI100
Answered from the entry's own figures: memory, which models fit, bandwidth, power and the card's class.
AMD Instinct MI100 has 32 GB of HBM2 at 1,229 GB/s. At INT8 a model's weights take about one byte per parameter, so the card holds roughly a 25B-parameter model with room for context; larger models need several cards or a lower precision.
From the catalog's estimates at INT8, Qwen 2.5 14B Instruct, Llama Nemotron Embed VL 1B V2, GLM Z1 9B 0414 and NVIDIA Nemotron Nano 12B V2 VL BF16 fit on a single AMD Instinct MI100 with their default context. The list on this page shows the estimated memory each takes; the capacity planner sizes any model against this card for your own context length, batch size and request rate.
1,229 GB/s. Bandwidth bounds how fast a model generates tokens, because every token reads the whole set of weights and the KV cache from memory; at this rate a 25B model at INT8 could be read on the order of 48 times a second on one card, before batching and framework efficiency.
AMD Instinct MI100 has a TDP of 300 W, with a maximum of 300 W, in the PCIe form factor. Budget the TDP per card plus host overhead when sizing a server's power and cooling.
AMD Instinct MI100 is a datacenter accelerator, meant for servers and multi-GPU serving, built on the CDNA 1 architecture and released in 2020. It has no multi-GPU interconnect, so a model must fit on one card or be split over the slower PCIe bus.
Specifications from the manufacturer's published material; a figure that is not published is shown as such, and a derived one is explained in the notes.
Added Jan 27, 2026 · Last updated Jan 27, 2026
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